As the size of semiconductor devices in VLSI circuits continues to shrink, the impact of contact resistance in device performance is becoming more important. Generally, when metal is in contact with doped silicon, such as at the contact to a transistor source or drain region or gate electrode, a Schottky barrier is formed at the interface. This Schottky barrier contributes to a higher contact resistance, thus decreasing device performance. Generally, higher contact resistance degrades drive current, which in turn limits device performance and speed, increases device heating, and causes other undesirable consequences.
One approach to lowering contact resistance is to increase the doping concentration of the semiconductor region to which contact is made, typically a transistor source or drain region or gate electrode, although the region could be a doped polysilicon resistor, a capacitor plate, or some other doped region. Traditionally, such regions are formed from a doped silicon region, e.g., a silicon or polysilicon layer that has been doped with impurities such as arsenic, phosphorous, boron, and the like. Generally, increasing the level of the impurity concentration impacts many device characteristics, including decreasing undesirable contact resistance. Silicon has limited impurity solubility, however, so the ability to decrease contact resistance by increasing the dopant concentration cannot proceed beyond the impurity solubility limits of the silicon. The impurity concentration level may have significant impact on other device characteristics as well, and hence the impact on contact resistance cannot be taken in isolation of other ways that the impurity concentration may affect device performance. This may further limit the ability to reduce contact resistance by increasing impurity concentration.
The use of a silicide layer for decreasing the contact resistance is also known. In conventional devices, a metal silicide layer is formed on the doped region to which contact is to be made. This silicide region is typically formed either by depositing a silicide layer (e.g., titanium silicide, tungsten silicide, cobalt silicide) on the silicon or polysilicon region to which contact is to be made (e.g., a source or drain region, a gate region, a doped polysilicon layer), or by converting a portion of the silicon or polysilicon region to a silicide (an in situ process by which a metal film is deposited on the region and wherein the metal and (poly)silicon interact to form a silicide in a subsequent thermal processing step).
As the trend toward smaller device geometries increases, coupled with the desire for still further improved device performance, the need exists for structures and methods that will allow for decreased contact resistance. This is particularly true for devices having gate lengths in the 90 nm and below range.